1. Field of the Invention
This invetnion relates generally to interlaced SPS CCD memories and more particularly to an improved configuration requiring only seven clock pulses.
2. Description of the Prior Art
Charge coupled device (CCD) memories for use in data processing system storage are well known in the art. The original Boyle and Smith concept (See Boyle et al., U.S. Pat. No. 3,858,232) appeared in the Bell System Technical Journal in April, 1970, Pages 587-593. Numerous subsequent publications and patents include an article entitled; "Charge Coupled Devices and Application", Solid State Technology, April, 1974, Pages 67-77 by J. E. Carnes and W. F. Kosonocky. The technical and patent literature describes various improvments to the original concepts and these teachings including the aforementioned published and patent literature are incorporated herein by reference.
In the field of high density and low power dissipation CCD's, a serial-parallel-serial (SPS) structure was described in Weimer, U.S. Pat. No. 3,763,480. In an SPS configuration, a data bit stream is injected into a serial CCD shift register from where it is transferred in parallel to a parallel storage register. The data can then be shifted in parallel through the parallel register, transferred in parallel to an output serial register, from where it is shifted out as a serial bit stream.
The foregoing SPS configuration had density constraints occasioned by the need for CCD's to have both transfer and storage sites. For example, assuming a two phase shift register, the storage of one bit of information requires not only a storage site but also a transfer site so that bits are actually stored in only one-half of the available sites. Assuming a two-phase serial CCD with eight sites, only four bits can be stored. When transferring from a serial to a parallel configuration, the channel width was made twice the required width so that only one-half of the potentially available storage sites in the parallel register could be utilized.
Density could be significantly improved by an interlaced serial-parallel-serial configuration. In an interlaced structure, all eight serial bits can be transferred in parallel through the parallel section, at least theoretically doubling the number of bits that can be stored in the parallel section. Such interlaced SPS configurations are described in Elmer et al., U.S. Pat. No. 4,007,446, as well as in U.S. Pat. Nos. 3,913,077, and 3,967,254. These three patents teach various clocking techniques and input/output register structures. The described techniques address various problems related to the advantageous implementation of an interlaced SPS CCD configuration.
A problem that remains unsolved by the aforementioned three patents is a requirement for an excessive number of clocks. For example, it would appear that U.S. Pat. No. 3,913,077 requires 10 clocks, U.S. Pat. No. 3,967,254 requires 13 clocks, and U.S. Pat. No. 4,007,446 requires not only 24 clocks, but additional buffer rows such as row 00 and row 34 for SPS buffering. On a semiconductor chip, every clock must be distributed to selected devices by conductors which, of necessity, occupy space on the semiconductor chip. These added conductors, usually formed by highly doped polycrystalline silicon and/or metallurgy, decrease the bit per unit area density of the CCD storage. Furthermore, the generation and processing of each clock pulse usually requires additional support circuitry which occupies semiconductor chip area further taking away from the space that is available for data bit storage.